This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-268849, filed Sep. 5, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, more particularly, to a level-shifting circuit.
2. Description of the Related Art
FIG. 24 is a circuit diagram showing a conventional level-shifting circuit (4-transistor type).
As shown in FIG. 24, the level-shifting circuit is constituted by input side NMOS f1 and f3 for receiving input signals D, ND (ND is a complementary signal of D), output side PMOS f4 cascade connected to the NMOS f1, and output side PMOS f2 cascade connected to the NMOS f3.
The inverse operation of such level-shifting circuit is terminated by inverting drain voltage (output signal Q) of the NMOS f3, and drain voltage (output signal NQ; NQ is a complementary signal of Q) of the NMOS f1, respectively, and inverting ON/OFF of the PMOS f4 receiving an output signal Q and the PMOS f2 receiving an inverted output signal NQ in a gate thereof. In this inverse operation, especially in its initial stage, the drain current of the part to become ON by inversion out of the drain currents of NMOS f1, f3, is required to be sufficiently larger than the drain current of the part to become OFF by inversion out of the drain currents of PMOS f2, f4.
Specifically, in the initial stage of the inverse operation, at least the following condition (1) is required between drain current Id1 of the NMOS f1 (or f3) and drain current Id2 of the PMOS f4 (or f2) cascade connected to the drain current Id1:
|Id1(Vgs=Vddxe2x88x92Vss)| greater than |Id2(Vgs=Vssxe2x88x92vcc)|xe2x80x83xe2x80x83(1)
In other words, under the following condition (2), the level-shifting circuit is not operated.
|Id1(Vgs=Vddxe2x88x92Vss)|xe2x89xa6Id2(Vgs=Vssxe2x88x92vcc)|xe2x80x83xe2x80x83(2)
For example, in case the maximum voltage vdd of the input signals D, ND is reduced to the level near threshold voltage of the NMOS f1, f3, the drain current Id1 of the NMOS f1 (or f3) decreases to make it difficult to satisfy the above condition (1) and the level-shifting circuit may not be operated.
Thus, in order to have the level-shifting circuit operate sufficiently, the above condition (1) is required to be satisfied.
In case the maximum voltage Vcc (Vcc greater than vdd) of the output signals Q, NQ is elevated, the drain current Id2 of the PMOS f4 (or f2) increases to make it difficult to satisfy the above condition (1) similarly and the level-shifting circuit may not be operated.
Accordingly, conventionally there has been a contrivance made to enlarge element sizes of the NMOS f1, f3, and the PMOS f2, f4, in order to satisfy the condition (1) above. For example, in the NMOS f1, f3, its gate width W is increased, and in the PMOS f2, f4, its gate length L is increased. By this step, the driving capacity of the NMOS f1, f3 is enhanced, and the drain current Id1 is enlarged. On the contrary, the drain current Id2 can be reduced.
Further, in order to satisfy the condition (1) above, a 6-transistor type level-shifting circuit as shown in FIG. 25 is contrived.
In the 6-transistor type level-shifting circuit as shown in FIG. 25, PMOS f13 or PMOS f14 suppresses the supply of the potential to the source of PMOS f12 or PMOS f14 in the initial stage of the inverse operation. For this reason, this transistor may have the drain current in the initial stage of the inverse operation smaller than that of the 4-transistor type level-shifting circuit shown in FIG. 24.
In the conventional level-shifting circuit, there may be the situation such that, in case the voltage ratio xe2x80x9cVcc/Vddxe2x80x9d between the voltage Vdd prior to the level-shifting and the voltage Vcc after the level-shifting is made larger by lowering the voltage Vdd of the input signals D, ND or elevating the voltage Vcc of the output signals Q, NQ, the level-shifting circuit fails to operate.
Accordingly, in order to dissolve this situation, contrivance is made to enlarge the element size of MOSFET which constitutes the level-shifting circuit.
However, in the field of the semiconductor integrated circuit device, there is a requirement of micronization and high integration, and there is a limit to satisfy the condition (1) described above only by the contrivance of enlarging the element size of the MOSFET.
Besides, contrivance is made of the 6-transistor type level-shifting circuit. In this 6-transistor type level-shifting circuit, in comparison with the 4-transistor type level-shifting circuit, the drain current Id2 in the initial stage of the inverse operation can be minimized to make it easier to satisfy the above condition (1).
However, as the 6-transistor type level-shifting circuit basically only suppresses the supply of the electric current to the source of the PMOS f4 or f2 in the initial stage of the inverse operation, there remains a limit.
A semiconductor integrated circuit device according to an embodiment of the present invention comprises: a level-shifting circuit configured to level-shift an input signal having a first amplitude to an output signal having a second amplitude different from the first amplitude, the level-shifting circuit having an input node in which the input signal is inputted and an output node in which the output signal is outputted; a current mirror circuit configured to charge or discharge the output node; and a switch circuit configured to operate the current mirror circuit during a period from the inversion of the input signal to the inversion of the output signal.